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12 Applied Instructions (High Speed Processing)
268
FXCPU Structured Programming Manual
[Basic & Applied Instruction]
12.4 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set
Function and operation explanation
1. 32-bit operation (DHSCS)
When the current value of a high speed counter of the device specified by becomes the comparison
value of the device specified by (for example, when the current value changes from "199" to "200" or
from "201" to "200" if the comparison value is K200), the bit device specified by is set to ON without
regard to the operation cycle. This instruction is executed after the counting processing in the high speed
counter.
Operation
When the current value of the high speed counter C235 changes from "99" to "100" or from "101" to "100",
Y010 is set to ON (output refresh).
Related instruction
The following instructions can be combined with high speed counters.
Instruction Instruction name
DHSCS High speed counter set
DHSCR High speed counter reset
DHSZ High speed counter zone compare
DHCMOV High speed counter move
DHSCT High speed counter compare with data table
Command input
Comparison value
Comparison source
DHSCS
EN
s1
s2
ENO
d
Output
destination
OUT_C_32
EN
CCoil
CValue
ENO
CC235
=
→
Set to ON
s1 s2 d
M8000
RUN
monitor
DHSCS
EN
s1
s2
ENO
d
K100
CN235
Y010 K100 =
→
Set to ON
CN235 Y010
OUT_C_32
EN
CCoil
CValue
ENO
CC235