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FX3G/FX3U/FX3UC Series Programmable Controllers
Programming Manual - Basic & Applied Instruction Edition
33 Extension File Register Control – FNC290 to FNC299
33.3 FNC292 – INITR / Initialize R and ER
33.3 FNC292 – INITR / Initialize R and ER
Outline
This instruction initializes (to “HFFFF” <K-1>) extension registers (R) in the RAM built in a PLC and extension file
registers in a memory cassette (flash memory) before data logging by LOGR (FNC293) instruction.
In FX
3UC PLCs former than Ver.1.30, use this instruction to initialize extension file registers (ER) before writing data to
them using SAVER (FNC291) instruction.
In FX
3UC PLCs Ver.1.30 or later and FX3U PLCs, INITER (FNC295) instruction is also provided to initialize (to
"HFFFF" <K-1>) only extension file registers (ER) in a memory cassette (flash memory) in units of sector.
→ For SAVER (FNC291) instruction, refer to Section 33.2.
→ For LOGR (FNC293) instruction, refer to Section 33.4.
→ For INITER (FNC295) instruction, refer to Section 33.6.
1. Instruction format
2. Set data
*1. When a memory cassette is not used, extension file registers (ER) are not initialized.
3. Applicable devices
Explanation of function and operation
1. 16-bit operation (INITR and INITRP)
“n” sectors of extension registers in the PLC’s built-in RAM starting from the one specified by and “n” sectors of
extension file registers in a memory cassette (flash memory) having the same device numbers are initialized (to
“HFFFF” <K-1>).
Initialization is executed in units of sector.
Operand Type Description Data Type
Device number of extension register and extension file register
*1
to be initialized
It is possible to specify only the head device number in a sector of extension registers.
16-bit binary
n Number of sectors of extension registers and extension file registers to be initialized
Oper-
and
Type
Bit Devices Word Devices Others
System User Digit Specification System User
Special
Unit
Index
Con-
stant
Real
Number
Charac-
ter String
Pointer
XYMTCSD
.b KnX KnY KnM KnS T C D R
U\G
V Z Modify K H E "
"P
33
n 33
P
FNC 292
INITR
Mnemonic Operation Condition
16-bit Instruction
5 steps
INITR
Mnemonic Operation Condition
Continuous
Operation
32-bit Instruction
⎯
⎯
INITRP
Pulse (Single)
Operation
S
S
S
FNC292
INITRP
S
n
Command
input