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Software Developer’s Manual 77
PCI Local Bus Interface
Max_Lat/Min_Gnt
1
The Ethernet controller places a very high load on the PCI bus during peak
transmit and receive traffic. In full duplex mode, it has a peak throughput
demand of 250 MB/sec. The peak delivered bandwidth on a 64-bit PCI bus at 33
MHz is 264 MB/sec, so the bus is fully saturated when transmit and receive are
operating simultaneously. In half duplex operation, the Ethernet controller has a
peak throughput demand of 125 MB/sec, which still puts an enormous load on
the PCI bus. Consequently, the Max_Lat should be small and is set to 00h, and
Min_Gnt is set to FFh indicating that the Ethernet controller requires a very high
priority and time slice.
Interrupt Pin
Read only register indicating which interrupt line (INTA# vs. INTB#) the
82546GB/EB uses. A value of 1b indicates that the 82546GB/EB uses INTA#
(as with all single-port Ethernet controllers). A value of 10b indicates that the
82546GB/EB uses INTB#.
For each separate device/function within the Ethernet controller, the value
reported here is based on the EEPROM Initialization Control Word 3 associated
with this controller, as well as whether both device/functions are enabled.
Provided both functions are enabled, then the value reported for each specific
function is based on the Interrupt Pin field of each Ethernet controller’s
Initialization Control Word 3.
If only a single internal device/function is enabled, then the value reported here
is 1b regardless of EEPROM configuration.
Interrupt Line Read write register programmed by software to indicate which of the system
interrupt request lines this Ethernet controller’s interrupt pin is bound to. See the
PCI definition for more details.
Table 4-3. Command Register Layout
1. This bit is a don’t care for the 82547GI/EI.
15 10 9 0
Reserved Command Bits
Bit(s) Initial Value Description
0 0b I/O Access Enable.
1 0b Memory Access Enable.
20b
Enable Mastering. Ethernet controller in PCI-X
mode is permitted to initiate a split completion
transaction regardless of the state of this bit.
3 0b Special Cycle Monitoring.