Filter
Top Products
320 Software Developer’s Manual
Register Descriptions
13.4.46 Receive Descriptor Control
RXDCTL (02828h; R/W)
This register controls the fetching and write-back of receive descriptors. The three threshold values
are used to determine when descriptors are read from and written to host memory. The values can
be in units of cache lines or descriptors (each descriptor is 16 bytes) based on the GRAN flag. If
GRAN = 0b (specifications are in cache-line granularity), the thresholds specified (based on the
cacheline size specified in the PCI header CLS field) must not represent greater than 31
descriptors.
Table 13-87. RXDCTL Register Bit Description
31 25 24 23 22 21 16 15 14 13 8 7 6 5 0
Reserved GRAN RSV WTHRESH RSV HTHRESH RSV PTHRESH
Field Bit(s)
Initial
Value
Description
PTHRESH 5:0 0b
Prefetch Threshold
Used to control when a prefetch of descriptors is considered. This
threshold refers to the number of valid, unprocessed receive
descriptors the Ethernet controller has in its on-chip buffer. If this
number drops below PTHRESH, the algorithm considers
prefetching descriptors from host memory. This fetch does not
happen unless there are at least RXDCTL.HTHRESH valid
descriptors in host memory to fetch. Value of PTHRESH can be in
either cache line units, or based on number of descriptors based
on RXDCTL.GRAN.
RSV 7:6 0b
Reserved
Reads as 0b.
Should be written as 0b for future compatibility.
HTHRESH 13:8 0b
Host Threshold
Provides the threshold of the valid descriptors in host memory.
A descriptors prefetch is performed each time enough valid
descriptors (TXDCTL.HTHRESH) are available in host memory,
no other DMA activity of greater priority is pending (descriptor
fetches and write backs or packet data transfers) and the number
of receive descriptors the Ethernet controller has on its on-chip
buffers drops below RXDCTL.PTHRESH. Value of HTHRESH
can be in either cache line units, or based on number of
descriptors based on RXDCTL.GRAN.
RSV 15:14 0b
Reserved
Reads as 0b.
Should be written as 0b for future compatibility.