Filter
Top Products
272 Software Developer’s Manual
Register Descriptions
GMII FIFO Register (82541xx and 82547GI/EI Only)
PFIFO (20d; R/W)
NOTES:
1. The default is determined by EEPROM bit SPD_EN.
2. The default is determined by EEPROM bit ADV10LU.
Table 13-40. GMII FIFO Register Bit Description
Field Bit(s) Description Mode HW Rst SW Rst
Buffer Size 3:0
An unsigned integer that stipulates the
number of write clocks to delay the read
controller after internal GMII’s tx_en is
first asserted. This “buffer” protects from
underflow at the expense of latency.
The maximum value that can be set is
13d or Dh.
R/W 0101b 0101b
Enable Speed-Up
Upon Cable
Reconnect
4
When set, the PHY advertises higher
speed than 10Base-T after reconnect of
the cable, even if the software
advertised only 10Base-T speed.
R/W Note 2 Note 2
Power Down On Link
Disconnect
5
When set, the PHY optimizes the power
consumption when the cable is
disconnected. The PHY gets back to
normal operation reconnect of the cable,
supporting Auto-Negotiation and parallel
detection.
R/W Note 1 Note 1
Reserved 7:6
Always read as 0b. Write to 0b for
normal operation.
R/W 00b 00b
FIFO Out Steering 9:8
00b, 01b: Enable the output data bus
from GMII FIFO to transmitters, drives
zeros on the output loop-back bus from
GMII FIFO to external application and to
DSP RX-FIFOs in test mode.
10b: Drive zeros on output bus from
GMII FIFO to transmitters, enable data
on the output loop-back bus from GMII
FIFO to external application and to DSP
RX-FIFOs in test mode.
11b: Enable the output data bus from
GMII FIFO to both transmitters and
loop-back bus.
R/W 00b 00b
Disable Error Out 10
When set, disables the addition of
under/overflow errors to the output data
stream on internal GMII’s tx_error.
R/W 0b 0b
Reserved 13:11
Always read as 0b. Write to 0b for
normal operation.
R/W 0b 0b
FIFO Overflow 14
Status bit set when read clock that is
faster than internal GMII’s gtx_clk
empties the FIFO mid packet. Increase
the buffer size.
RO/
LH
0b 0b
FIFO Underflow 15
Status bit set when read clock that is
slower than internal GMII’s gtx_clk has
allowed the FIFO to fill to capacity mid
packet. Decrease buffer size.
RO/
LH
0b 0b