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Software Developer’s Manual 305
Register Descriptions
This feature operates by initiating a countdown timer upon successfully receiving each packet to
system memory. If a subsequent packet is received BEFORE the timer expires, the timer is re-
initialized to the programmed value and re-starts its countdown. If the timer expires due to NOT
having received a subsequent packet within the programmed interval, pending receive descriptor
writebacks are flushed and a receive timer interrupt is generated.
Setting the value to 0b represents no delay from a receive packet to the interrupt notification, and
results in immediate interrupt notification for each received packet.
Writing this register with FPD set initiates an immediate expiration of the timer, causing a
writeback of any consumed receive descriptors pending writeback, and results in a receive timer
interrupt in the ICR.
Receive interrupts due to a Receive Absolute Timer (RADV) expiration cancels a pending RDTR
interrupt. The RDTR countdown timer is reloaded but halted, so as to avoid generation of a
spurious second interrupt after the RADV has been noted, but might be restarted by a subsequent
received packet.
13.4.31 Receive Interrupt Absolute Delay Timer
1
RADV (0282Ch; RW)
Warning: It is strongly recommended that the Delay Timer field of this register not be used. For any
application requiring an interrupt moderation mechanism, it is recommended that the Interrupt
Throttling Register (ITR) be used instead. ITR provides a more direct interrupt solution than
RADV. In addition, Intel software device drivers use ITR instead of RADV. Refer to the
82546EB
Gigabit Ethernet Controller Specification Update
or 82546GB Gigabit Ethernet Controller
Specification Update
for additional details.
If the packet delay timer is used to coalesce receive interrupts, the Ethernet controller ensures that
when receive traffic abates, an interrupt is generated within a specified interval of no receives.
During times when receive traffic is continuous, it may be necessary to ensure that no receive
remains unnoticed for too long an interval. This register can be used to ENSURE that a receive
interrupt occurs at some predefined interval after the first packet is received.
1. Not applicable to the 82544GC/EI.
31 30 16 15 0
Reserved Delay Timer
Field Bit(s)
Initial
Value
Description
Delay Timer 15:0 0b
Receive absolute delay timer measured in increments of 1.024 µs (0b =
disabled).
Reserved 31:16 0b Reserved. Reads as 0b.