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338 Software Developer’s Manual
Register Descriptions
Table 13-94. ALGNERRC Register Bit Description
13.7.3 Symbol Error Count
SYMERRS (04008h; R)
Counts the number of symbol errors between reads. The count increases for every bad symbol
received, whether or not a packet is currently being received and whether or not the link is up. This
register only increments in internal SerDes mode (TBI mode for the
82544GC/EI).
Table 13-95. SYMERRS Register Bit Description
13.7.4 RX Error Count
RXERRC (0400Ch; R)
Counts the number of packets received in which I_RX_ER was asserted by the PHY. In order for a
packet to be counted in this register, it must pass address filtering and must be 64 bytes or greater
(from <Destination Address> through <CRC>, inclusively) in length. If receives are not enabled,
then this register does not increment. In internal SerDes mode (TBI mode for the
82544GC/EI),
this register increments on the reception of
/V/ codes.
31 0
AEC
Field Bit(s)
Initial
Value
Description
AEC 31:0 0b Alignment error count
31 0
SYMERRS
Field Bit(s)
Initial
Value
Description
SYMERRS 31:0 0b Symbol Error Count