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378 Software Developer’s Manual
General Initialization and Reset Operation
Table 14-3. Signal Functions Not Supported
14.5.3 Avoiding GMII Test Mode(s)
Note that the Ethernet controller contains a set of test modes that use this interface for component
manufacturing and/or diagnostic test. To avoid accidental engagement of unexpected test mode(s)
when using the external GMII (or TBI), the TEST_GMII[2:0] test pins must remain de-asserted
(low) and the TEST_DM_N pin must remain de-asserted (high).
14.5.4 MAC Configuration
The Ethernet controller MAC operates in a GMII/MII mode when operating with the internal PHY;
this mode is similar to the GMII/MII mode of the standalone 82543 MAC components and others.
In GMII/MII mode, the MAC operates assuming use of a GMII/MII interface communication,
variable duplex & speed configuration (unless forced or auto-detected). For the Ethernet
controller, to use this external interface as a GMII/MII interface and have the MAC operate in this
GMII/MII Mode, the LINK_MODE must be set to 01b.
It is likely that the MAC might be required to be configured in a forced-duplex configuration, as no
means is provided (either the MDI/O access or direct PHY-to-MAC signaling) of any duplex
configuration that might be negotiated between the attached Ethernet controller/transceiver and its
link partner.
The MAC can further be required to be configured in a forced-speed configuration, as no direct
speed indication is available via the external interface (compared to the SPD_IND signals provided
by the internal PHY). The Auto-Speed detection (ASD) can be potentially useful in automatically
calculating and configuring a speed setting based in the interface signals that are provided.
The MAC is unable to provide any access to MII Management registers through the MDIC register,
as no explicit MDI/O signals are included in this interface. However, it is possible that software-
definable pins (SDP) can be capable of providing the necessary access capability.
Signal Function Ramifications
MII Management Interface (PHY Register Access)
MDC Management Data Clock
No support/access to MII register set.
MDI/O Management Data I/O
Direct PHY Indications to MAC
FDX PHY-negotiated full/half duplex indication
Can limit use to specific known duplex
setting.
SPD_IND PHY-negotiated speed (10/100/1000 Mbps)
Can limit use to specific known speed or
require use of auto-speed detection.