Hitachi NJI-350B Video Game Controller User Manual


 
Chapter 7 Programming
7-4
Table 7.4 List of procedures for creating a program
Create new program Modify Test operation, adjustment
Item
Off-line Off-line On-line On-direct
Out-line of opera-ting procedure
OK
N
G
Start
Select off-line
Initialize PLC
CPU type: Specify H-302
Memory type: Specify RAM-04H
Create I/O assignment
Create program
Program check
Save in FD, etc.
End
OK
N
G
Start
Select off-line
Regenerate from FD, etc.
When utilizing a program created
in another H-series
CPU type: Specify H302
Memory type: Specify RAM-04H
Modify I/O assignment
Modify program
Change the name and
save in FD, etc.
Program check
End
OK
OK
OK
NG
NG
*1
Start
Select on-line
Regenerate from FD, etc.
Initialize the CPU when
running it for the first
time(right after purchase, etc.)
(PLC CPU)
CPU error check
Conduct test operation
Operation check
To modificatio
n
End
Transfer program
OK
OK
N
G
Start
Select on-line
Transfer program
(CPU
PLC)
Select on-direct
Conduct test operation
Modify program (modify
during RUN, etc.)
Operation check
Enter in FD, etc.
End
Situation
When creating a new
program
When modifying a program When transferring a created
program to the CPU for the
first time
When modifying a program
during test operation
Point
A program can be created
without executing MICRO-
EH.
When using a program that
was used in another H-series,
specify H-302 as the CPU
type.
When performing CPU error
check, make sure the I/O
assignment matches the
loaded module. (The loading
read function can be used to
match them forcibly.)
To enter the on-direct mode,
match the contents in the
CPU’s memory and personal
computer’s memory. The
modified contents will be
reflected in both the
computer memory and CPU
memory.
*1: Set the flow size to 0 for memory assignment.
If a program transfer is performed by specifying the flow size, the message “Cannot execute: Operation error” is displayed, and
a peripheral unit remain as WRITE occupied. In this case, either cancel the occupy state from LADDER EDITOR of the
peripheral unit or by re-entering the CPU power.