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Standard Commands for Programmable Instruments (SCPI)
89
*CLS
Meaning and Type
Clear Status
Device Status
Description
This command causes the following actions (see "Status Reporting" for descriptions of all registers):
♦
Clears the following registers without affecting any corresponding Enable Registers or Transition Filters:
◊
Standard Event Status Event Register
◊
Operation Status Event Register
◊
Questionable Status Event Register
◊
Status Byte Register
♦
Clears the Error Queue
♦
Forces a previously executed
*OPC command to appear as if it had been completed. It does not do this with the *OPC?
command (see *OPC? for more details).
♦
If
*CLS immediately follows a program message terminator (<NL>), then the output queue and the MAV bit are also
cleared.
Command Syntax *CLS
*ESE
Meaning and Type
Event Status Enable
Device Status
Description
This command programs the Standard Event Status Enable register bits. The programming determines which events of the
Standard Event Status Event register (see
*ESR?) are allowed to set the ESB (Event Summary Bit) of the Status Byte
register. A "1" in the bit position enables the corresponding event. All of the enabled events of the Standard Event Status
Event Register are logically ORed to cause the ESB (bit 5) of the Status Byte Register to be set. See "Status Reporting" for
descriptions of all three registers.
Bit Configuration of Standard Event Status Enable Register
Bit Position
7 6 543210
Condition PON 0 CME EXE DDE QYE 0 OPC
Bit Weight 128 64 32 16 8 4 2 1
CME = Command error; DDE = Device-dependent error; EXE = Execution error; OPC = Operation complete; PON =
Power-on; QRY = Query error
If *PSC is programmed to zero, *ESE causes a write cycle to nonvolatile memory. Non volatile memory has
a finite maximum number of write cycles. Programs that repeatedly cause write cycles to nonvolatile
memory can eventually exceed the maximum number of write cycles and cause the memory to fail.