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8 – Language Dictionary
136
*SAV
This command stores the present state of the dc source to the specified location in non-volatile memory.
Up to 4 states can be stored. If a particular state is desired at power-on, it should be stored in location 0.
It will then be automatically recalled at power turn-on if OUTPut:PON:STATe is set to RCL0. Use
*RCL to retrieve instrument states.
Command Syntax
*SAV <NRf>
Parameters
0 | 1 | 2 | 3
Example
*SAV 3
Related Commands
*RCL *RST
CAUTION: *SAV causes a write cycle to nonvolatile memory. Nonvolatile memory has a finite
maximum number of write cycles. Programs that repeatedly cause write cycles to
nonvolatile memory can eventually exceed the maximum number of write cycles and
cause the memory to fail.
*SRE
This command sets the condition of the Service Request Enable Register. This register determines which
bits from the Status Byte Register (see *STB for its bit configuration) are allowed to set the Master
Status Summary (MSS) bit and the Request for Service (RQS) summary bit. A 1 in any Service Request
Enable Register bit position enables the corresponding Status Byte Register bit and all such enabled bits
then are logically ORed to cause Bit 6 of the Status Byte Register to be set.
When the controller conducts a serial poll in response to SRQ, the RQS bit is cleared, but the MSS bit is
not. When *SRE is cleared (by programming it with 0), the dc source cannot generate an SRQ to the
controller. The query returns the current state of *SRE.
Command Syntax
*SRE <NRf>
Parameters
0 to 255
Power-on Value
see *PSC
Example
*SRE 20
Query Syntax
*SRE?
Returned Parameters
<NR1> (register binary value)
Related Commands
*ESE *ESR *PSC
CAUTION: If *PSC is programmed to 0, the *SRE command causes a write cycle to nonvolatile
memory. Nonvolatile memory has a finite maximum number of write cycles. Programs
that repeatedly cause write cycles to nonvolatile memory can eventually exceed the
maximum number of write cycles and cause the memory to fail.
*STB?
This query reads the Status Byte register, which contains the status summary bits and the Output Queue
MAV bit. Reading the Status Byte register does not clear it. The input summary bits are cleared when
the appropriate event registers are read. The MAV bit is cleared at power-on, by *CLS' or when there is
no more response data available.