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TR bits can be used as many times as required as long as the same TR bit is
not used more than once in the same instruction block. Here, a new instruc-
tion block is begun each time execution returns to the bus bar. If more than
eight branching points requiring that the execution condition be saved are
necessary in a single instruction block, interlocks, which are described next,
must be used.
When drawing a ladder diagram, be careful not to use TR bits unless neces-
sary. Often the number of instructions required for a program can be reduced
and ease of understanding a program increased by redrawing a diagram that
would otherwise required TR bits. With both of the following pairs of dia-
grams, the versions on the top require fewer instructions and do not require
TR bits. The first example achieves this by merely reorganizing the parts of
the instruction block; the second, by separating the second OUTPUT instruc-
tion and using another LOAD instruction to create the proper execution con-
dition for it.
Instruction 1
0000
Instruction 2
0001
TR 0
Instruction 2
0000
Instruction 1
0001
Instruction 1
0000
Instruction 2
0003
TR 0
0001
0004
0002
0001 0003
0000
0004
0002
0001
Instruction 1
Instruction 2
Note TR bits are only used when programming using mnemonic code and are not
necessary when inputting ladder diagrams directly, as is possible from a
GPC. The above limitations on the number of branching points requiring TR
bits and considerations on methods to reduce the number of programming
instructions still hold.
The Ladder Diagram Section 4-3