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Receive and Transmit Description
48 Software Developer’s Manual
3.3.7.1 TCP/IP Data Descriptor Command Field
The Command field provides options that control checksum offloading and TCP segmentation
features along with some of the generic descriptor processing features.
Table 3-18. Command Field (TDESC.DCMD) Layout
7 6 5 4 3 2 1 0
IDE VLE DEXT
RSV
RPS
a
a. 82544GC/EI only.
RS TSE IFCS EOP
TDESC.DCMD Description
IDE (bit 7)
Interrupt Delay Enable
When set, activates the transmit interrupt delay timer. Hardware loads a countdown
register when it writes back a transmit descriptor that has RS and IDE set. The value
loaded comes from the IDV field of the Interrupt Delay (TIDV) register. When the
count reaches 0, a transmit interrupt occurs if enabled. Hardware always loads the
transmit interrupt counter whenever it processes a descriptor with IDE set even if it is
already counting down due to a previous descriptor. If hardware encounters a
descriptor that has RS set, but not IDE, it generates an interrupt immediately after
writing back the descriptor. The interrupt delay timer is cleared.
VLE (bit 6)
VLAN Enable
When set, indicates that the packet is a VLAN packet and the hardware should add
the VLAN Ethertype and an 802.1q VLAN tag to the packet. The Ethertype should
come from the VET register and the VLAN data comes from the special field of the TX
descriptor. The hardware in that case appends the FCS/CRC.
Note that the CTRL.VME bit should also be set. If the CTRL.VME bit is not set, the
Ethernet controller does not insert VLAN tags on outgoing packets and it sends
generic Ethernet packets. The IFCS controls the insertion of the FCS/CRC in that
case.
VLE is only valid in the last descriptor of the given packet (qualified by the EOP bit).
DEXT (Bit 5)
Descriptor Extension
Must be 1b for this descriptor type
RPS
RSV (bit 4)
Report Packet Sent
RPS is used in cases where software must know that a packet has been sent on the
wire, not just that it has been loaded into the 82544GC/EI controller’s internal packet
buffer.
When set, hardware defers writing the DD bit in the status byte until the packet has
been sent, or transmission results in an error such as excess collisions. Hardware
can continue to pre-fetch data from descriptors logically after the one with RPS set,
but does not advance the head pointer or write back any other descriptors until it has
sent the packet with RPS set.
For a TCP Segmentation context, the RPS bit indicates to the 82544GC/EI that the
descriptor status should only be written back once all packets that make up the given
TCP Segmentation context had been sent.
This bit is reserved and should be programmed to 0b for all Ethernet controllers
except the 82544GC/EI.
RS (bit 3)
Report Status
When set, tells the hardware to report the status information for this descriptor as
soon as the corresponding data buffer has been fetched and stored in the controller’s
internal packet buffer.