Intel PCI Video Game Controller User Manual


 
Software Developer’s Manual xiii
Contents
13.8.5 Receive Data FIFO Packet Count ....................................................366
13.8.6 Transmit Data FIFO Head Register..................................................366
13.8.7 Transmit Data FIFO Tail Register ....................................................367
13.8.8 Transmit Data FIFO Head Saved Register ......................................367
13.8.9 Transmit Data FIFO Tail Saved Register .........................................368
13.8.10 Transmit Data FIFO Packet Count ...................................................368
13.8.11 Packet Buffer Memory......................................................................369
14 General Initialization and Reset Operation..................................................371
14.1 Introduction........................................................................................................371
14.2 Power Up State .................................................................................................371
14.3 General Configuration .......................................................................................371
14.4 Receive Initialization..........................................................................................372
14.5 Transmit Initialization.........................................................................................373
14.5.1 Signal Interface ................................................................................376
14.5.2 GMII/MII Features not Supported.....................................................377
14.5.3 Avoiding GMII Test Mode(s).............................................................378
14.5.4 MAC Configuration ...........................................................................378
14.5.5 Link Setup ........................................................................................379
14.6 PHY Initialization (10/100/1000 Mb/s Copper Media) .......................................380
14.7 Reset Operation ................................................................................................381
14.8 Initialization of Statistics ....................................................................................384
15 Diagnostics and Testability ...............................................................................385
15.1 Diagnostics........................................................................................................385
15.1.1 FIFO State........................................................................................385
15.1.2 FIFO Data.........................................................................................385
15.1.3 Loopback..........................................................................................385
15.2 Testability ..........................................................................................................386
15.2.1 EXTEST Instruction..........................................................................387
15.2.2 SAMPLE/PRELOAD Instruction .......................................................387
15.2.3 IDCODE Instruction..........................................................................387
15.2.4 BYPASS Instruction .........................................................................387
A Appendix (Changes From 82544EI/82544GC) ............................................389
B Appendix (82540EP/EM and 82545GM/EM Differences).........................391