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Software Developer’s Manual 135
Power Management
6.3.2.3 Transition From D0a to D3 and Back with PCI Reset
Figure 6-4. Transition From D0a to D3 and Back with PCI Reset
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Diagram # Notes
1
Writing a 11b to the Power State field of the Power Management Control/Status Register (PMCSR) transitions
the Ethernet controller to D3.
2 The system can delay an arbitrary amount of time between setting D3 mode and asserting RST#.
3
In 66 MHz or PCI-X
a
modes the system must assert RST# before stopping the PCI clock. It may assert RST#
without stopping the clock.
For the 82541PI/GI/EI and 82540EP, If CLK_RUN# is enabled, then they do not require a continuous clock
during this time, but does require that the system drive the clock in response to CLK_RUN# assertion.
4 Upon assertion of RST# the Ethernet controller floats all PCI pins except PME# and goes to “Dr” state.
5
In 66 MHz or PCI-X modes, the PCI 2.2 and 2.3 specification requires the system to start the PCI clock 100 µs
before deassertion of RST#. In 33 MHz systems the PCI clock can start and stop at any time independent of
RST#.
6 The deassertion edge of RST# causes the EEPROM to be re-read and Wakeup disabled.
7
Synchronizing the clock circuits and circuit adjustments require up to 512 PCI clocks before the Ethernet
controller drives PCI signals and responds to PCI transactions.
8 For the 82544GC/EI, O_PWR_STATE is set to 01b if APM Wakeup is enabled, 00b otherwise.
9 The system can delay an arbitrary time before enabling memory access.
10
Writing a 1b to the Memory Access Enable or I/O Access Enable bit in the PCI Command Register transitions
the Ethernet controller from D0u to D0 state.
For the 82544GC/EI, writing a 1b to the Memory Access Enable or I/O Access Enable bit in the PCI Command
Register transitions the Ethernet controller from D0u to D0 state and asserts both PWR_STATE outputs.
a. Not applicable to the 82541xx, 82547GI/EI, or 82540EP/EM.