Filter
Top Products
Software Developer’s Manual 7
Architectural Overview
Architectural Overview 2
2.1 Introduction
This section provides an overview of the PCI/PCI-X Family of Gigabit Ethernet Controllers. The
following sections give detailed information about the Ethernet controller’s functionality, register
description, and initialization sequence. All major interfaces of the Ethernet controllers are
described in detail.
The following principles shaped the design of the PCI/PCI-X Family of Gigabit Ethernet
Controllers:
1. Provide an Ethernet interface containing a 10/100/1000 Mb/s PHY that also supports 1000
Base-X implementations.
2. Provide the highest performance solution possible, based on the following:
— Provide direct access to all memory without using mapping registers
— Minimize the PCI target accesses required to manage the Ethernet controller
— Minimize the interrupts required to manage the Ethernet controller
— Off-load the host processor from simple tasks such as TCP checksum calculations
— Maximize PCI efficiency and performance
— Use mixed signal processing to assure physical layer characteristics surpass specifications
for UTP copper media
3. Provide a simple software interface for basic operations.
4. Provide a highly configurable design that can be used effectively in different environments.
The PCI/PCI-X Family of Gigabit Ethernet Controllers architecture is a derivative of the 82542
and 82543 designs. They take the MAC functionality and integrated copper PHY from their
predecessors and adds SMBus-based manageability and integrated ASF controller functionality to
the MAC
1
. In addition, the 82546GB/EB features this architecture in an integrated dual-port
solution comprised of two distinct MAC/PHY instances.
1. Not applicable to the 82544GC/EI or 82541ER.