Intel PCI Video Game Controller User Manual


 
188 Software Developer’s Manual
PHY Functionality and Features
11.4.2 D3 State, No Link Required (copper only)
Each time the MAC transitions to a D3 or D0u power-state with no link required (wakeup disabled
and no manageability enabled), the PHY enters its IEEE power-down mode, consuming the least
amount of power possible. When powered-down, the PHY does not perform any form of Energy
Detection, and does not generate any energy (NLPs) on the wire itself.
MAC transitions back to D0 power-states, either through explicit system/software mechanisms or
by hardware reset operations, return the PHY back to a functional power-state. This will also re-
initiate an auto-negotiation attempt advertising all speeds possible (10/100/1000 Mbps)
1
, reverting
to an Energy Detect state if unsuccessful in establishing link-up.
11.4.3 D3 Link-Up, Speed-Management Enabled (copper only)
If the MAC is configured for PHY power management (CTRL.EN_PHY_PWR_MGMT = 1b) and
the PHY is linked at 1000 Mbps, then upon MAC transitions to D3 or D0u power-states where link
IS required (either wakeup or manageability are enabled), the PHY re-initiates an Auto-
Negotiation operation, advertising only 10/100 Mbps capability. This results in D3 operation at a
lower-speed link and a reduced power level.
If a wakeup, management operation, or other system event causes the MAC to revert to fully-
operational D0 state, the PHY initiates another Auto-Negotiation operation, advertising all 10/100/
1000 Mbps speed capability, in order to return to maximum-speed operation.
11.4.4 D3 Link-Up, Speed-Management Disabled (copper only)
If the MAC is configured for no PHY power management (CTRL.EN_PHY_PWR_MGMT = 0b),
and the MAC transitions to D3 power-states where link is required for either wakeup or
manageability, then the PHY simply remains operational at its current line speed, without initiating
a new Auto-Negotiation operation. This configuration is not recommended, since D3 power
consumption at 1000 Mbps exceeds 20 mA Vaux.
1. Half duplex not supported.