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SentinelRAID 170 Installation and Hardware Reference Manual
Fault Tolerance A-2
A.2.5 Controller Architecture
The controller is developed from Infortrend's PowerPC-500133 ASIC architecture, a
third-generation, 64-bit controller design that efficiently eliminates internal bottlenecks.
The controller's high performance derives from a state-of-the–art PowerPC
®
750CXe
RISC microprocessor, which provides a 64-bit 133MHz path to SDRAM. The 500133
integrates SDRAM control, CPU peripheral, dual 64-bit PCI buses, and hardware XOR
functions. The ASIC provides 133MHz operating frequency for CPU and DRAM
interfaces, and 66MHz for PCI interfaces. Two 64-bit 66MHz PCI buses can operate
independently to maximize the performance.
A.3. Fault Tolerance
A.3.1 Global and Local Spares
Both global and local (dedicated) spares are supported. The controller(s) will
automatically disconnect from a failed drive and start to rebuild data on the spare drive.
The spare drive will then replace the failed drive.
A.3.2 Hot-swapping of Drives
A failed drive can be exchanged without turning off the system or interrupting its smooth
operation. Once the failed drive is replaced, the data will be rebuilt in the background.
Hot-swapping is supported through the automatic disconnection from a failed drive and
the detection of a reserve drive. All of these failure recovery procedures are completely
transparent to the host.
A.3.3 S.M.A.R.T. Support
S.M.A.R.T (Self Monitoring Analysis and Reporting Technology) is supported with
configurable reaction schemes. You may select different reaction schemes for immediate
prevention against S.M.A.R.T.-detected errors. Available options include: detect only,
clone and replace, and perpetual clone. A faulty drive can be cloned to an active spare
upon the discovery of errors.
A.3.4 Other Fault Tolerant Features
Other comprehensive failure management features on the SR controller include:
• Automatic bad-block assignment
• Background rebuilding
• Verify-after-write support on normal writes, rebuild writes, and/or RAID
initialization writes
• Regeneration of parity of logical drives in the background