Tests And Error Messages
Order In Which POSTs Occur
Chapter 4
87
11h Load alternate registers with initial POST
values
12h Restore CPU control word during warm boot
13h Initialize PCI bus mastering devices PCI Mast. Init.
14h Initialize keyboard controller
16h BIOS ROM checksum BIOS Check sum
17h Initialize cache before memory autosize
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset programmable interrupt controller
20h Test DRAM refresh RAM Refresh Test
22h Test 8742 keyboard controller Keyb. Ctrl. Test
24h Set ES segment register to 4GB
26h Enable A20 line
28h Autosize DRAM Memory Detection 3
29h Initialize POST memory manager
2Ah Clear 512KB base RAM
2Ch
RAM failure on address line
a
RAM Add. Failure
2Eh RAM failure on data bits xxxx1 of low byte of
memory bus
RAM Data Low
2Fh Enable cache before system BIOS shadow
30h RAM failure on data bits xxxx1 of high byte
of memory bus
RAM Data High
32h Test CPU bus-clock frequency
33h Initialize POST dispatch manager
36h Warm start shut down
38h Shadow system BIOS ROM Shadow BIOS ROM
3Ah Autosize cache
3Ch Advanced configuration of chipset registers
3Dh Load alternate registers with CMOS values
42h Initialize interrupt vectors
45h POST device initialization
Table 4-4 POST Checkpoint Codes (Continued)
Checkpoint
Code
POST Routine Description
MaxiLife LCD
Display Message
Beep
Codes
