System Board
Memory Controller Hub (82850)
Chapter 2
40
MCH Overview
The MCH provides the processor interface, memory interface, AGP interface and hub
interface in an Intel 850 chipset platform. The MCH supports two channels of Direct
RDRAM operating in lock-step. It also supports 4x AGP data transfers and 2x/4x AGP
fast writes. The primary host interface enhancements include:
• Source synchronous double pumped address
• Source synchronous quad pumped data
• System bus interrupt delivery
The MCH supports a 64B cache line size. One processor is supported at a system bus
frequency of 100 MHz (400 MHz Data Bus). It supports 32-bit host addresses, letting the
processor address the entire 4GB space of the MCH’s memory address space. The MCH
also provides an eight-deep In-Order Queue that supports as many as eight outstanding
pipelined address requests on the host bus.
Host-initiated I/O signals are subtractively decoded to the hub interface. Host-initiated
memory cycles are positively decoded to AGP or RDRAM and are again subtractively
decoded to the hub interface.
AGP semantic memory accesses initiated from AGP to DRAM are not snooped on the
host bus. Memory accesses initiated from AGP using PCI semantics and accesses from
the hub interface to DRAM are snooped on the system bus. Memory access whose
addresses lie within the AGP aperture are translated using the AGP address translation
table, regardless of the originating interface.
Accelerated Graphics Port (AGP) Bus Interface
A controller for the AGP Pro 1.5V slot is integrated in the MCH. The AGP interface
supports 1x/2x/4x AGP signaling and 2x/4x fast writes. AGP semantic cycles to the
DRAM are not snooped on the host bus. PCI semantic cycles to DRAM are snooped on
the host bus. The MCH supports PIPE# or SBA{7.0} AGP address mechanisms, but not
both simultaneously. Either the PIPE# or the SBA{7.0] mechanism must be selected
during system initialization. Both upstream and downstream addressing is limited to
• Power management:
— SMRAM space remapping to A0000h -
BFFFFh (128KB).
— Extended SMRAM space above 256MB,
additional 128KB, 256KB, 512KB, 1MB
TSEG from top of memory, cacheable
(cacheability controlled by processor)
— ACPI 1.0 compliant power management
— APM 1.2 compliant power management
• Arbitration:
— Distributed arbitration model for
concurrency support
— Concurrent operations of system, hub
interface, AGP, and memory buses
supported through a dedicated
arbitration and data-buffering logic
• 615 OLGA MCH package • I/O device support:
— I/O Controller Hub (ICH2)
Feature Feature
