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Chapter 4 Remote Interface Reference
The SCPI Status Registers
102
The SCPI Status Registers
All SCPI instruments implement status registers in the same way. The status
system records various instrument conditions in three register groups: the
Status Byte register, the Standard Event register, and the Questionable Status
register groups. The status byte register records high-level summary
information reported in the other register groups. The diagram on the
subsequent pages illustrates the SCPI status system used by the power supply.
What is an Event Register?
An event register is a read-only register that reports defined conditions within
the power supply. Bits in an event register are latched. Once an event bit is set,
subsequent state changes are ignored. Bits in an event register are
automatically cleared by a query of that register (such as
*ESR?
or
STAT:QUES:EVEN?
) or by sending the
*CLS
(clear status) command. A reset
(
*RST
) or device clear will not clear bits in event registers. Querying an event
register returns a decimal value which corresponds to the binary-weighted sum
of all bits set in the register.
What is an Enable Register?
An enable register defines which bits in the corresponding event register are
logically ORed together to form a single summary bit. Enable registers are both
readable and writable. Querying an enable register will not clear it. The
*CLS
(clear status) command does not clear enable registers but it does clear the
bits in the event registers. To enable bits in an enable register, you must write
a decimal value which corresponds to the binary-weighted sum of the bits you
wish to enable in the register.