8279/8279·5
board Mode, the Auto·lncrement flag
(AI)
and the RAM
address
bits
(AAA) are irrelevant. The 8279 will automati·
cally
drive the data bus for each subsequent read (Ao=
0)
in the same sequence in which the data first entered the
FIFO. All subsequent reads will
be
from the FIFO
until
another command is issued.
In the Sensor Matrix Mode, the RAM address
bits
AAA
select one
of
the 8 rows
of
the Sensor RAM.
If
the
AI
flag
is set (AI = 1), each successive read will
be
from the sub·
sequent row
of
the sensor RAM.
Read Display RAM
Code:
1 0
11
11
1
AliA
I A I A I A 1
The
CPU
sets up the 8279 for a read
of
the Display RAM
by
first
writing
this
command. The address bits AAAA
select one
of
the 16 rows
of
the Display RAM.
If
the
AI
flag is set (AI = 1),
this
row address will
be
incremented
after
each
following
read
or
write to the Display RAM.
Since the same counter
is
used for both reading and
writing,
this
command sets the next read
or
write
address and the sense
of
the Auto·lncrement mode for
both operations.
Write
Display RAM
Code:
11
I 0 I 0 I AI I A I A I A I A 1
The
CPU
sets up the 8279 for a write to the Display RAM
by
first
writing
this
command.
After
writing the com·
mand with
Ao=
1,
all subsequent writes with
Ao=
0 will
be
to
the Display RAM. The addressing and Auto·
Increment
functions
are identical to those
for
the Read
Display RAM. However,
this
command does not affect
the source
of
subsequent Data Reads; the
CPU
will read
from whichever RAM
(Display
or
FIFO/Sensor) which
was last specified. If, indeed, the Display RAM was last
specified, the Write Display
RAM
will, nevertheless,
change the next Read
location.
Display
Write Inhibit/Blanking
The IW Bits can be used
to
mask nibble A and nibble B
in applications requiring separate
4·bit display ports. By
setting
the IW flag (IW = 1) for one
of
the ports, the port
becomes marked so that entries
to
the Display RAM
from the
CPU
do
not affect that port. Thus,
if
each nibble
is
input
to a BCD decoder, the
CPU
may write a
digit
to
the Display RAM
without
affecting the other
digit
being
displayed. It is important
to
note that bit
Bo
corresponds
to
bit
Do
on the
CPU
bus, and that bit
A3
corresponds
to
bit
0
7
,
If the user
wishes
to
blank the display, the BL flags are
available for each nibble. The last Clear command issued
determines the code
to
be
used as a
"blank."
This code
defaults
to all zeros after a reset. Note that both BL
flags must be set
to
blank a display formatted with a
single 8-bit port.
Clear
The Cobits are available in this command to clear all rows
of
the Display RAM to a selectable blanking code as fol-
lows:
1 0 AB = Hex 20 (0010 0000)
1 1 All
Ones
r~
':
'
AU
'''0'
{X
"
Doo"''',,{
Enable
clear
display
when
= 1 (or by
CA
= 1)
During the time the Display
RAM
is being cleared ("'160
flS),
it may not
be
written to. The most
significant
bit
of
the
FIFO status word is set during
this
time. When the Dis·
play
RAM
becomes available again, it automatically
resets.
If the C
F
bit
is asserted
(C
F
= 1), the FIFO status is
cleared and the interrupt
output
line is reset. Also, the
Sensor
RAM
pointer is set to row
O.
C
A
,
the Clear All bit, has the combined effect
of
Co and
C
F
; it uses the
CD
clearing code on the Display RAM and
also clears FIFO status. Furthermore, it resynchronizes
the
internal
timing
chain.
End Interrupt/Error Mode Set
Code:
For the sensor matrix modes this command
lowers the
IRQ line and enables further writing into RAM. (The IRQ
line would
have been raised upon the detection of a
change
in
a sensor value. This would have also inhibited
further writing into the
RAM
until reset).
For the N-key
rollover mode - if the E bit
is
programmed
to
'"1"'
the chip will operate
in
the special Error mode. (For
further details.
see
Interface Considerations Section.)
Status Word
The status word contains the FIFO status, error,
and
display unavailable signals. This word
is
read by the
CPU
when
Ao
is high and
CS
and
RD
are low.
See
Interface
Considerations for more detail on status word.
Data
Read
Data
is
read when
Ao.
CS and
RD
are all low. The source
of
the data
is
specified by the
Read
FIFO or
Read
Display
commands. The trailing edge
of
RD
will cause the address
of the
RAM
being read to
be
incremented if the Auto-
Increment flag
is
set.
FIFO reads always increment (if
no
error occurs) independent of AI.
Data Write
Data that
is
written with
Ao.
CS
and
WR
low
is
always
written to the Display RAM. The address
is
specified by the
latest
Read
Display or Write Display command. Auto-
Incrementing
on the rising edge of
WR
occurs if
AI
set by
the
latest display command.
9-74
AFN·Q0742A-QS
