8205
HIGH SPEED 1 OUT
OF8
BINARY DECODER
•
1/0
Port
or
Memory Selector
• Simple
Expansion - Enable Inputs
•
Hig"h
Speed Schottky Bipolar
Technology
-
18
ns Max Delay
•
Directly Compatible with
TTL
Logic
Circuits
• Low Input Load. Current -
0.25
mA
Max,
1/6 Standard
TTL
Input Load
• Minimum Line Reflection - Low
Voltage Diode Input Clamp
•
Outputs Sink
10
mA Min
• 16·Pin Dualln·Line Ceramic
or
Plastic
Package
The Intel'" 8205 decoder can
be
used for expansion
of
systems which utilize input ports, output ports, and memory
components with active
low chip select input. When the
8205
is enabled, one
of
its 8 outputs goes
"low",
thus a single
row
of
a memory system is selected. The 3·chip enable inputs on the
8205
allow easy system expansion. For very large
systems,
8205
decoders can
be
cascaded such that each decoder can drive 8 other decoders for arbitrary memory
expansions.
The
8205 is packaged in a standard 16-pin dual in-line package, and its performance is specified over the temperature
range
of
oDe
to
+75°e,
ambient.
The
use
of
Schottky barrierdlode clamped transistors
to
obtain fast switching speeds
results in higher performance than equivalent devices made with a gold diffussion process.
PIN CONFIGURATION
LOGIC SYMBOL
Ao
16
V.cc
Ao
A,
15
0
0
A,
A2
3
14
0,
A2
E,
4 13
°2
8205
8205
E2
5 12
0
3
E3
6
11
0.
E,
0,
10
°5
E2
GRD
8
0
6
EJ
ADDRESS
ENABLE
OUTPUTS
PIN
NAMES
Ao
A,
A,
E,
E,
E3
0
1
2 3
•
0 6
)
L
L
L L L H
L
H H
H H H
H
H
H
L L
L L
H H L H H H
H H H
AO·
A2
ADDRESS INPUTS
L
Ii
L L L H H H
L
H H
H
H
H
H H
L L L H H H H
L
H
H H H
L L H
L L H H H H H L H H H
E
,.
E3
ENABLE INPUTS
00·
0,
DECODED OUTPUTS
H
L
H
L L H H H H H H
L H H
l
H H
L L H H H H H H H
L
H
H H H
L
L H H H H H H H
H L
X X X
L
L
L H
H
H H H H H H
X X X H L
L
H H
H
H
H
H H H
X
X
X L
H
L H H H H H H
H H
X X X H H
L H H H H H H H H
X X X H
L
H H H H H H H
H H
X X
X
L
H
H
H H H H
H
H H H
X X X H H H H H H H H H
H
H
8-18
AFN-00204B-ol
