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A
Accumulator
This directive
may
be used
to
display
and/or
alter
the
contents
of
the
simulated accumulator. A space
or
comma
follow-
ing
the
A will display
in
binary,
the
contents
of
the
simulated accumulator. This
or
the
A may be followed
either
by a
new value
to
be
entered,
or
by a carriage
return
to
end
the
directive.
C
Carry/Link
This directive may be used
to
display
and/or
alter
the
contents
of
the
simulated Carry/Link bit.
The
use
of
this direct-
ive
is
the
same as
for
A.
Xn
Index
This directive
may
be used
to
display
and/or
alter
the
contents
of
anyone
or
pair
of
the
simulated index registers. If
a space
or
comma
follows
the
X,
all 16 index registers are displayed (in decimal). Otherwise, if
the
(decimal)
number
n
is
followed by a space, index register n
may
be displayed
and/or
altered as in A. If
the
number
n
is
followed
by
a
comma,
slash,
or
period, index pair
number
n
may
be displayed (in decimal)
and/or
altered as a unit.
(Index
registers
2n
and
2n
+ 1 are handled
together
as a single 8-bit number.)
S
Stack
pointer
This directive may be used
to
display
and/or
alter
the
contents
of
the
subroutine
stack pointer.
The
current
loca-
tion
counter
is
the
one
pointed
to
by this pointer. This
pointer
is
incremented by JMS instructions and
decremented
by
BBl
instructions.
l
location
Counter
This directive may be used
to
display
and/or
alter
the
contents
of
the
current
location
counter.
Note
that
altering
the
value
of
the
stack
pointer
will cause a
different
register
to
be
current
location
counter.
E Examine Everything
This directive
combines
the
display
functions
of
the
C,
A,
S,
l,
R,
and X directives.
All
four
program
counters
in
the
stack are displayed.
No
modification
is
possible.
R RAM/ROM selection
This directive may be used
to
display
and/or
modify
the
simulated
memory
chip/location
seleetion. A space
or
comma
after
the
R
types
out
an 11-bit binary
number,
of
which
the
most-significant 3 bits represent
the
command
line
selection effected
by
the
last
DCl
instruction, and
the
least-significant 8 bits represent
the
contents
of
the
index pair
as last used
by
an SRC instruction.
B
Breakpoint
This directive may be used
to
display
and/or
modify
the
contents
of
the
breakpoint
register.
The
simulated
execution
will always be
interrupted
before processing
the
instruction
pointed
to
by
the
breakpoint.
If
the
breakpoint
points
to
the
second
byte
of
a
two-byte
instruction, no
breakpoint
action
will occur during
instruction
simulation.
W When
This directive may be used
to
display
and/or
alter
the
contents
of
the
simulated
sync
cycle
counter.
This
is
a 12-bit
(decimal)
counter
used
to
tally
the
number
of
instruction cycles used during
instruction
simulation.
T Trace
This directive causes
the
simulation program
to
begin simulated execution
of
the
test
program, beginning
at
the
address
in
the
current
location
counter.
If instruction
execution
simulation
is
interrupted
by a
breakpoint,
the
keyboard
BREAK key,
or
an illegal instruction,
the
T directive will cause
the
program
to
resume
where
it left off,
just
as if
the
program was never
interrupted,
except
insofar as program parameters
or
registers
were
modified while
interrupted.
The
basic
format
of
the
trace listing
is
pppp:iiiiiiii c aaaa rr
where
pppp
is
the
decimal location
counter;
iiiiiiii
is
the
binary representation
of
the
(first
byte
of
the)
instruction
being simulated; c
is
the
resultant carry/I ink bit; aaaa
is
the
resultant
accumulator
value; and rr
is
the
resultant
(decimal)
index
or
index pair used
in
the
instruction. (value,
not
index number)
Any
or
all
of
the
last
three
numbers
may
be
omitted
on
instructions which
do
not
reference
their
respective registers.
N Non-trace
This directive
is
identical
to
the
T directive,
except
that
execution
proceeds
without
tracing.
o
Options
This directive may be used
to
display
and/or
alter
the
current
option
status
bits.
This
is a 4-bit binary
number
with
the
following significance;
1
Input,
Output,
and CPU
test
instructions are
executed
directly
when
this
bit
is
on,
instead
of
typing
out
on
the
teletype
the
port
number
and
then
typing
or
accepting
the
data.
10
No
interrupt
for
subroutine
stack overflow
or
underflow will
occur
when
this
bit
is
on.
1000
Unconditional jumps and
subroutine
jumps
to
ROM
page 0 (chip 0) are
executed
directly instread
of
interpretively, permitting
direct
byte
I/O during checkout.
3