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2.3 Timing
Table 2-3: Timing Specifications
Write Cache Enabled
Time to Erase (ATA Secure Erase)
Notes:
1. Based on MLC NAND
2. Device measured using IOMETER 08, Queue depth set to 32 for NCQ
3. Sector Read/Write latency measured up ton 4K block size (512B/sector = 1 Block), random access
4. Sequential IOPS cover the entire range of valid logical block addresses (LBA’s). Measurements are
performed on a full drive (all LBA’s have valid content)
2.3.1 STANDBY IMMEDIATE Command
The Power On to Ready time assumes a proper shutdown (power removal
preceded by STANDBY IMMEDIATE command. A STANDBY IMMEDIATE
before power down always performs a graceful shutdown and does not require
the use of the hold-up circuit. Note that SMART attribute 174 "Unexpected Power
Loss" records the number of non-graceful power cycle events.
The timings for when a STANDBY IMMEDIATE is issued to when it is completed
are shown in the table below.
Table 2-4: STANDBY IMMEDIATE Timing
STANDBY IMMEDIATE to WE completed
