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7 - Programming the DC Source
88
The MSS Bit
This is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service
Request Enable register. MSS is set whenever the dc source has one or more reasons for requesting
service. *STB? reads the MSS in bit position 6 of the response but does not clear any of the bits in the
Status Byte register.
The RQS Bit
The RQS bit is a latched version of the MSS bit. Whenever the dc source requests service, it sets the
SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller does a
serial poll, RQS is cleared inside the register and returned in bit position 6 of the response. The
remaining bits of the Status Byte register are not disturbed.
The MAV Bit and Output Queue
The Output Queue is a first-in, first-out (FIFO) data register that stores dc source-to-controller messages
until the controller reads them. Whenever the queue holds one or more bytes, it sets the MAV bit (4) of
the Status Byte register.
Determining the Cause of a Service Interrupt
You can determine the reason for an SRQ by the following actions:
Step 1 Determine which summary bits are active. Use:
*STB? or serial poll
Step 2
Read the corresponding Event register for each summary bit to determine which events
caused the summary bit to be set. Use:
STAT:QUES:EVEN?
STAT:OPER:EVEN?
ESR?
When an Event register is read, it is cleared. This also clears the corresponding
summary bit.
Step 3 Remove the specific condition that caused the event. If this is not possible, the event
may be disabled by programming the corresponding bit of the status group Enable
register or NTR|PTR filter. A faster way to prevent the interrupt is to disable the
service request by programming the appropriate bit of the Service Request Enable
register
Servicing Operation Status and Questionable Status Events
This example assumes you want a service request generated whenever the dc source switches to the CC
(constant current) operating mode, or whenever the dc source's overvoltage, overcurrent, or
overtemperature circuits have tripped. From figure 7-7, note the required path for a condition at bit 10
(CC) of the Operation Status register to set bit 6 (RQS) of the Status Byte register. Also note the
required path for Questionable Status conditions at bits 0, 1, and 4 to generate a service request (RQS) at
the Status Byte register. The required register programming is as follows: